The present disclosure is related to thin film transistors, and more specifically to a thin film field effect transistor structure with dual semiconductor and insulator layers providing improved device stability and performance.
A field effect transistor (FET) is an electronic device in which current is permitted to flow between a source and a drain terminal in a conductive region, or channel, created by a voltage bias established across a gate terminal and the source terminal. Varying the voltage at the gate varies the channel size and conductivity, allowing the gate to control the flow of current between source and drain.
A thin film transistor (TFT) is typically a FET which is formed over an insulating substrate and in which the source, drain, and gate, as well as the layer in which the channel is established are formed from thin layers of material. The substrate is often glass, ceramic, plastic, fiberglass, or similar insulating material. The source, drain, and gate terminals are often formed of a patterned metal. The channel layer is typically a semiconductor, and commonly silicon (Si). Certain characteristics of the TFT are determined by the crystalline state of the semiconductor layer, which may be single crystal Si, polycrystalline Si, or amorphous Si. As used herein, polycrystalline, re-crystallized, amorphous materials, and suspension and polymer materials are collectively referred to as disordered materials.
Thin film FET designs and characteristics are well known. Thin film FETs are generally combined with other thin film devices to form operational circuits. For example, several thin film FETs may be interconnected to form switching circuits for display or detector panels, peak detection or transition detection circuits, clock doubling circuits, etc.
In the case of amorphous, polymer, and similar disordered semiconductor applications, individual thin film FETs exhibit an undesirable instability during operation. For example, the semiconductor layer presents carrier traps which fill as a function of time and current. As the number of positively charged carriers increases at the gate terminal due to the application of a gate voltage, the number of negative carriers trapped in the channel region increases. However, as a stable, fixed voltage continues to be applied to the gate terminal, the number of negative carriers trapped in the channel increases with time. This time-based trapping means that even for a fixed gate voltage, the channel current characteristics change over a relatively short period of time. This means that in a wide variety of FET devices, such as a circuit in which a signal should issue when a fixed threshold of charge is detected or exceeded, the threshold will in fact drift over time.
Another way to view this problem is to plot the electric field strength in the semiconductor layer against gate voltage at several different times, as shown in FIG. 1. At time t1, a certain gate voltage v produces a certain field strength ε1. However, at a later time t2, that same applied gate voltage v produces a field strength ε2 reduced by an amount Δε as compared to the field produced by that voltage at time t1. This change is field strength over time reduces carrier mobility in the channel, and hence reduces the current sensed at the drain in response to the gate voltage.
There have been numerous efforts to address this problem of time-instability. One such effort involves developing circuits with numerous thin film FETs such that instability is effectively cancelled out among the FETs. One problem with this approach is that additional FETs increase the size and power demands of the device circuitry, contrary to the desired objective of reducing device size and power consumption. Another problem is that as the number of FETs increases, so does the likelihood that one or more of the devices will fail and render the circuit inaccurate or inoperative. Still further, each FET has its own non-linearity characteristics, meaning accurate device performance is difficult to predict. Therefore, there is a need in the art for a disordered material-based thin film FET with reduced instability, which can be manufactured without significantly changing manufacturing techniques, without requiring the use of unorthodox materials, and which can otherwise easily be adapted to form an element of a known circuit.